Product Engineering Lead
ULVAC
Valrico, Florida, United States
Brian Joseph Coppa, Ph.D. is a Product Engineering Lead at ULVAC focused on deposition and plasma etch/clean wafer process equipment solutions for leading-edge semiconductor fabs. He has two decades of microelectronics industry experience in process engineering and business development from positions at: Micron/Intel, ASM, Tokyo Electron and EMD Electronics/Merck and as a consultant to numerous other companies across the overall supply chain. He has authored over 17 US and foreign patent publications and numerous technical journal articles, which have received many prestigious citations globally. Most notably, he co-patented the 1st self-aligned double patterning (SADP) used in production for IC shrinks & developed the key enabling atomic layer deposited (ALD) spacer process. SADP, also referred to as multi-patterning, has been critical over the last 2 decades for the semiconductor industry roadmap to continue microchip scaling. Brian is a Senior Member of the Institute of the Electrical and Electronics Engineer (IEEE) Society in addition to SPIE. Brian has been part of the leadership team for the SEMI Smart Manufacturing Initiative since its inception in 2018 and is a co-chair for the subcommittee entitled, "Accelerating Sustainability with Smart Manufacturing," which is leveraging Industry 4.0 best practices to publish an industry roadmap as a guide for device-making facilities. His doctorate and master's are in materials science engineering from North Carolina State University and he has a B.S. in physics from the University of Arizona. Also, Brian was a Research Professor in Electrical Engineering at Arizona State University part-time over a 2 year period.
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SEMI Smart Sustainability Roadmap: Blueprint for Device Makers
Wednesday, July 10, 2024
2:35pm – 3:05pm PDT