Account Technologist Director Applied Materials San Jose, California, United States
Discussions on the need for heterogenous integration (HI) of chiplets to overcome the limitations of the Moore’s law and the Von Neumann architecture has been around for a some time now, but adoption of the technology hasn’t yet met expectations partly due to yield concerns and cost. However, the growth in AI and high performance computing technology’s increasing need to accelerate power, performance, area, cost and time to market (PPACtTM) is finally bringing HI into mainstream discussions. Current HI solutions utilize a combination of TSV, microbumps, hybrid bonding, TDV, and interposer technologies including both Si and organic. While the industry has successfully brought these HI technologies to market, further innovation to scale interconnection will be critical to continuously extend this technology. Challenges will include scaling hybrid bonding to sub-micron scale, finding solutions for power limits on TSVs and using new technology to resolve thermal issues. This presentation will look at the overall trend and challenges for using HI technologies and incorporating them into future 3D architecture.
