In our current era, 2D scaling is slowing dramatically. We are in the world of design technology co-optimization or DTCO, where cleverly rearranging transistor elements and the other ingredients of the logic cells is giving us more and more of the shrink benefit. To make progress, we now need to pilot new materials and combinations of materials that are more difficult to work with. At the nanoscale, the interfaces between these materials can have surprising physical and chemical properties that are unlike their bulk properties. This requires us to develop new knowledge about the materials and the materials integration schemes.
With digital twins, sensors, and AI to detect hidden correlations between process recipe variables and on-wafer results, human engineers can use the power of AI to drive the semiconductor roadmap at a fast enough pace to keep up with the performance needs of AI computing.
