Reliability testing is an indispensable tool for evaluating the lifetime of electrical components. To satisfy the latest technology developments in automotive and communication applications, the reliability requests of some key semiconductor packages are increasing. In parallel with the higher performance demand of the advanced electrical components, a shortening of new device development time is also needed. Among the list of JEDEC standard reliability stress tests, temperature cycling (TC) is one of the most challenging and requires the most time to complete. This study is to evaluate the possibility of establishing an accelerated degradation method which can be correlated with the JEDEC standard temperature cycling test.
Four different approaches were investigated: 1. thermal shock under the same temperature range as the standard JEDEC temperature cycling condition but with much faster temperature ramp up and down speed, 2. temperature cycling under a wider temperature range (specifically with a higher upper temperature) but keeping the same ramp up and down speed as the JEDEC standard temperature cycling test, 3. 3-point bending test with defined mechanical stress applied onto the components at different temperatures, 4. temperature cycling under the standard JEDEC defined condition, but the chip in the component was bonded onto a shifted position on the substrate in order to achieve higher stress. Modeling and simulations were used to select the new bonding position that induces the most stress to the chip. All approaches were conducted using a QFN package. After thermal cycling, acoustic scans and cross sections with ion milling were used to detect the component degradation status. At the same time, stress simulations were conducted for all four approaches to understand the possible mechanism of different approaches.
The results indicate that approach 1, thermal shock tests, did accelerate the component degradation. However, the failure mode is not consistent with that after JEDEC standard temperature cycling tests. Approach 2, temperature cycling tests with wider temperature range (higher upper temperature), shows a similar failure mode to standard temperature cycling. However, the degradation time is similar with the standard JEDEC temperature cycling tests with no accelerated results. Approach 3, 3-point bending tests, were conducted at room temperature and -65°C with 30 secs per cycle. The tests are up to 5000 cycles and no failure was observed yet. Further tests are ongoing to determine the number of cycles needed to reach the break point and failure mode using this method. Approach 4, temperature cycling under the JEDEC standard condition with the component chip bonding position shifted, shows the same failure mode as that after the JEDEC standard temperature cycling test with normal chip bonding position. The degradation also appeared after much fewer temperature cycles. This indicates that approach 4 is a promising approach to accelerate temperature cycling testing while keeping a consistent degradation mechanism. It can be potentially used to screen different package designs and packaging materials.
