CEO
Sigenic
Singapore, Singapore
Tan Boon Siong (“BS”), CEO of Sigenic Pte Ltd. (B.Sc Hons Mechanical Engineering – Adelaide University Australia)
BS has established a reputation for developing innovative solutions aimed at improving semiconductor manufacturing productivity through predictive monitoring. His company, Sigenic Pte. Ltd. is now providing innovative solutions that are directly addressing long-standing machine reliability issues, thereby leading to significant reductions in yield loss and improvements in machine uptime/reliability. The solutions have the capability to be applied across different departments to improve the overall performance of wafer manufacturing machines. Some of Sigenic’s major clients have already adopted Sigenic’s solutions on a “must-have” basis with the intent of applying them globally across all their manufacturing sites. On this basis, Sigenic’s solutions have the potential to set new standards for reducing yield loss and improving efficiency and performance across the whole Semicon manufacturing industry.
Before Sigenic, BS was employed as a researcher at Nanyang Technological University (NTU), Singapore. During his time with NTU, he concentrated on developing a real-time condition monitoring method with advanced modeling features. His research contributed significantly to enhancing the efficiency and reliability of condition monitoring, establishing his reputation as a forward-thinking innovator in the field.
Prior to his academic role, BS made significant contributions during his 11 years of industry experience at a prominent Taiwanese Semicon company. As a Senior Staff Engineer in the thin film department, he led a team of engineers to maintain and improve machine uptime, provided expert advice on process defect troubleshooting and reduction, and managed module cost drivers to meet improvement targets. His accomplishments in this position are noteworthy. He is the inventor of a US patent for a wafer cleaning apparatus, and his work led to increasing wafer planarization machine’s uptime from 75% to 86.5%, improving throughput by 47%, and generating cost benefits exceeding $10 million per annum. His contributions to yield improvement, such as scratch and residue reduction and removal rate stability control, further underscore his technical prowess and innovative approach.
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Advancing Predictive Maintenance Capabilities for Semiconductor Wafer Production Tool
Wednesday, July 10, 2024
4:50pm – 6:00pm PDT