We present a printed method to fabricate submicron electrical interconnects via electrohydrodynamic jet (e-jet) printing, and an automation framework to interconnect nanomodular devices using computer vision and search algorithms. Compared with other printed electronics fabrication techniques, E-jet printing offers the advantages of high resolution, compatibility with a wide range of ink and substrate materials, and drop-on-demand capability. This work utilizes metal colloid-based inks and comprehensively studies e-jet printing process parameters, such as voltage signal, stage speed, and multi-layering, and post-print annealing conditions, such as temperature and duration, to understand their effects on interconnect resolution and electrical resistivity. Interconnects fabricated from Au nanoink and annealed at 250 ℃ achieve minimum line width of 300 nm, minimum pitch of 600 nm, and line resistivity of 2.3 × 10-5 Ω·cm. These capabilities provide promising opportunities to directly contact and interconnect nanoscale devices to create customizable, high performance, and heterogeneous circuits. We demonstrate the fabrication of depletion-load NMOS inverters by wiring lithography-defined modular metal-oxide-semiconductor field effect transistors (MOSFETs) with lengths of 20 µm on silicon-on-insulator (SOI) wafers. Through optimizing process parameters and understanding interface dynamics, we create inverter circuits from multiple wired MOSEFETs using optimized Au interconnect, and the circuits exhibit excellent voltage transfer characteristics. While preprogrammed interconnect patterns are sufficient for wiring regularly arrayed devices, modular components in hybrid circuits can be irregularly distributed with changing layouts. Manually locating and registering each device’s location and adjusting the interconnect pattern is inefficient and unscalable. To address this limitation, we develop a high-throughput and versatile method for automatically identifying substrate layout and designing interconnect patterns. Identification of devices on a substrate is achieved through in situ high-resolution imaging and computer vision algorithms that detect device contours and extract location and orientation. Pattern planning employs search algorithms that incorporate process and functional constraints. The resulting integrated system enables automatic wiring of multiple MOSFETs with large tilting angles and preserved device performance. In summary, this work develops submicron printing capability and an automated circuit interconnection framework. The resolution, speed, versatility, and cost-effectiveness of the developed system provides a platform for the fabrication of nanoscale, on-demand, high-throughput, and hybrid electronics.
