IRIIS: Infrastructure for Real-time Inspection of Image Sensors​

Our work focuses on enhancing image sensor testing systems by optimizing packet processing at line speed to meet increasing industry demands. We developed an optimized software stack leveraging CPU, GPU, and multi-gigabit NICs, achieving significantly higher throughput and better ACK response times compared to existing methods. Our system must meet stringent requirements related to costs, physical component placement, and high signal quality, which current technologies alone cannot achieve. Key performance targets include TCP/IP communication between DT and DP, achieving 80Gbps/connection, and minimizing TCP ACK response times for system stability and maximum performance.

Benchmarks compared CPU and GPU-centric models, with the optimized system achieving a maximum throughput of 92Gbps, nearly doubling the throughput compared to comparable tech stacks. The CPU-centric model utilized DPDK for packet processing, reducing memory copies and leveraging AVX-512 for data extraction. A real-time patched Linux kernel was employed to minimize network jitter. The GPU-centric model used NVIDIA's DOCA for direct memory access between NIC and GPU, supporting high-speed data transfer and processing.

The optimized TCP/IP protocol and RT-patched Linux kernel implementation achieved significant advancements in real-time image sensor testing technology. Future work will explore distributing DP functionality into a central DP cluster with an intra-optical fiber network to meet growing demands and higher throughput requirements of the image sensor market. This approach aims to provide greater flexibility, scalability, and enhanced overall performance of the test systems.