Scan diagnosis has been used localize defect suspects and guide failure analysis (FA) over several technology nodes. For leading process nodes (ex. 5nm and below), electrical fault isolation (EFI) and physical failure analysis have become even more challenging due to the small feature sizes with more complex transistor structures leading to increasing fault modes. The introduction of backside power rails in silicon devices in emerging processes will provide additional challenges because optical EFI techniques can be severely limited in their ability to isolate defect locales. Improving scan diagnosis outcomes are essential to both improving the quality of the end product as well as ensuring product yield. In this presentation, we will demonstrate how defects in scan chains are used to analyze yield limiters and are relied upon to ramp yield for new technology nodes and new products. The fewer suspects that scan chain diagnosis produces (higher diagnosis resolution), the quicker and more efficient the FA cycle time. The gains observed are mainly due to the reduced need for complex fault isolation for these highly resolved diagnosis reports. To achieve these goals, advances in chain diagnosis technology have been made by improving the ability to diagnose defects in global control signals such as set, reset and clocks, defects in the logic that can affect scan chain shifting and even diagnosing defects at the transistor-level of scan cells can significantly enable quicker yield ramp for new technology nodes. In the presence of techniques like backside power rails in semiconductor devices where optical EFI is limited, new chain diagnosis with enhanced resolution can play a crucial role in alleviating the pressures on PFA to improve yield ramp by providing highly localized defect locations for root cause analysis.