Applying Artificial Intelligence in Fab Technology Co-Optimization (FTCO™)
The latest generations of semiconductor and photonic integrated circuits (ICs) often include billions of components connected in three dimensions by "wires", local interconnects and vias. ICs are fabricated by depositing and etching different layers of semiconducting, conductor and dielectric materials on a semiconductor substrate or wafer; the patterns that form devices and interconnect are transferred lithographically by exposing layers of photoresist through a mask (patterning). Typically, semiconductor fabrication requires a high degree of automation and integration of complex, specialized equipment in ultra-clean fabrication facilities or “fabs”. As the industry scales, it requires better process control and integration to provide acceptable yields. Process control is further complicated when transferring an established semiconductor process flow to a different fab or to different pieces of equipment in the same fab. There is also a need for better tools and methods. All of these contribute to improved device yield and performance, while also providing greater productivity through reduction in time required for flow optimization, as well as reduced material and labor costs. The common approach to optimizing a fabrication process involves process and fab engineers creating and setting up Design of Experiments (DoEs) using a trial-and-error approach. The experiments are realized in silicon running wafers. The resulting wafers are analyzed to understand whether the process is meeting the desired targets. This approach often leads to costly iterations since wafer fabrication is both expensive and time-consuming. Typically, it can take weeks to months of experimentation, depending on what process parameters are not meeting their targets. The new approach which is covered in this presentation and is already in production use today, leverages artificial intelligence (AI) and machine learning (ML) to generate an accurate simplified model of a fabrication step. The approach involves using TCAD digital models of a fab process (digital twin) that consider the actual physics and chemistry involved. This digital twin model is used partially to test and analyze using the same DoE methodology, but without the need to fabricate multiple wafers, thus saving the cycle times and costs associated with the fabrication. Silvaco’s expertise in process and device simulation with its Technology Computer Aided Design (TCAD) platform, combined with ML driven statistical analysis are the key components of a new AI-based process technology solution for fabs that can drastically cut cost and design time. This solution ties the fabrication of wafers to simulation via the digital twin models, a process called Fab Technology Co-Optimization (FTCO™).
The FTCO flow includes: • A data visualization module, providing engineers with firsthand data trends; a regression module using a neural network engine to digitally model the target device based on the number of input features and performance parameters • An optimization module to find an optimal condition for the digitally modeled target device • A design of experiment (DoE) module to execute advanced DoE iterative search algorithms to produce more complete digital models based on the optimal conditions until an accurate model of the target device is generated.