Patterning Solutions to Break Stochastic Tradeoffs

Extreme ultraviolet (EUV) lithography has emerged as a pivotal technology enabling advanced semiconductor device scaling. Its integration into high volume manufacturing (HVM) of semiconductor ICs commenced with 7nm node logic and is now in qualification for an expanding array of lithographic steps at 5/3/2nm logic and 10nm class DRAM processes, underscoring its critical role in pushing the boundaries of device miniaturization.

In EUV lithography, there exists a fundamental tradeoff between resist stochastics and the overall cost of the lithography process. Efforts to mitigate the resist stochastics often entail increased exposure doses and raise the cost of EUV exposure. Breaking this tradeoff is critical for leveraging EUV’s inherent imaging efficiency and minimizing overall manufacturing costs.

We present here a suite of innovative patterning solutions tailored for extreme ultraviolet lithography, reducing the tradeoffs posed by resist stochastics, dimensional control, overlay and defectivity. We discuss advanced techniques including dry resist- based processing (deposition and development), post lithography resist modification and repair, and application of novel film solutions for exposure dose, line width roughness, and overlay. Implementation of these cutting-edge patterning solutions provides novel capabilities for breaking the tradeoff of resist stochastics and lithography cost, expanding the applications that can take advantage of leading edge EUV solutions.