SEMI U
Pete Sandow
Engineer
This course, about the device yield-related aspects of the Silicon Wafer is designed to give engineers working in yield improvement, as well as all process engineers and others who are involved in specifying Silicon in IC and MEMS devices, a working knowledge of the defects associated with the Silicon that arise from the vendor as well as those generated through device processing.
Throughout the course, practical knowledge of specific silicon defect and yield-related manufacturing examples will be introduced through a series of Short, one page "Applications Notes" covering topics of interest. A method to distinguish between bulk and surface stacking faults, methods to add gettering to SOI wafers, how to reduce high temperature leakage currents through the use of EPI In MEMS processing, and improved dimension control through the use of SOI wafers will also be discussed during this training.
All personnel who want to gain a fundamental understanding of how the Silicon wafer impacts device process yields, including: Yield Improvement Engineers, Process Engineers, Quality Engineers involved with Silicon, and Supply Chain Management are encouraged to complete this training.