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Wednesday, Jul 10th
9:00am – 12:20pm PDT
Test Vision Session 1: RF and Power Test Innovation
Location: Moscone South, Exhibition Level Room 9
Session Moderator (TV): Adrian Kwan – Advantest America Inc.
Test
Wednesday, Jul 10th
9:00am – 9:10am PDT
Opening Remarks
Location: Moscone South, Exhibition Level Room 9
Session Moderator (TV): Rich L. Dumene – Renesas Electronics Corporation
Test
Wednesday, Jul 10th
9:10am – 9:20am PDT
Test Vision Program Overview
Location: Moscone South, Exhibition Level Room 9
Session Moderator (TV): Stuart Pearce – AEM
Test
Wednesday, Jul 10th
9:20am – 9:50am PDT
Best ATE Paper of 2023: Award and Presentation
Location: Moscone South, Exhibition Level Room 9
Session Moderator (TV): Paul Berndt – Microsoft Corporation
Speaker (TV): Alberto Berizzi – TECHNOPROBE
Speaker (TV): Xin-Reng Foo – AMD
Test
Wednesday, Jul 10th
9:50am – 10:50am PDT
Keynote: The Rise of AI-Enhanced Test Engineering: Transforming Challenges into Opportunities
Location: Moscone South, Exhibition Level Room 9
Keynote Speaker (TV): Keith Schaub, MSEE – Advantest
Test
Wednesday, Jul 10th
10:50am – 11:05am PDT
High-efficiency,Low-cost Power IC(SPS) Test Solution Based on Multi-Task Technology
Location: Moscone South, Exhibition Level Room 9
Speaker (TV): Liu Huipeng – AccoTEST
Test
Wednesday, Jul 10th
11:05am – 11:20am PDT
High Multi-site Gallium Nitride MOSFET Test
Location: Moscone South, Exhibition Level Room 9
Speaker (TV): Eugene LIN – Chroma ATE
Speaker (TV): Jeff Lee – Chroma ATE Inc
Test
Wednesday, Jul 10th
11:20am – 11:35am PDT
Achieving single suspect chain diagnosis in the age of backside power
Location: Moscone South, Exhibition Level Room 9
Speaker (TV): Jayant C. D'Souza – Siemens DISW
Test
Wednesday, Jul 10th
11:35am – 11:50am PDT
Challenges in testing SiC and GaN semiconductors
Location: Moscone South, Exhibition Level Room 9
Speaker (TV): Higor Batagin – SPEA S.p.A.
Test
Wednesday, Jul 10th
11:50am – 12:05pm PDT
50% development time reduction by disciplined deployment of best practice methodologies
Location: Moscone South, Exhibition Level Room 9
Speaker (TV): David Ducrocq – TERADYNE/SEG
Test
Wednesday, Jul 10th
12:05pm – 12:20pm PDT
Session 1 Review + Raffle
Location: Moscone South, Exhibition Level Room 9
Session Moderator (TV): Adrian Kwan – Advantest America Inc.
Test
Wednesday, Jul 10th
1:30pm – 3:00pm PDT
Test Vision Session 2: AI Test Initiatives and Innovation
Location: Moscone South, Exhibition Level Room 9
Session Moderator (TV): Trent Weaver – Teradyne
Test
Wednesday, Jul 10th
1:30pm – 1:45pm PDT
Revolutionizing AI Chip Testing with AI-Driven Solutions
Location: Moscone South, Exhibition Level Room 9
Speaker (TV): Ira Leventhal – Advantest America, Inc.
Test
Wednesday, Jul 10th
1:45pm – 2:00pm PDT
Test program conversion using AI generative large language models
Location: Moscone South, Exhibition Level Room 9
Speaker (TV): Eugene LIN – Chroma ATE
Test
Wednesday, Jul 10th
2:00pm – 2:15pm PDT
Cryogenic Wafer-Scale Characterization of Superconducting Resonators for Improved Fabrication Yield
Location: Moscone South, Exhibition Level Room 9
Speaker (TV): Brandon W. Boiko – FormFactor Inc.
Test
Wednesday, Jul 10th
2:15pm – 2:30pm PDT
Provenance of Data: Why existing test data is not sufficient for AI training
Location: Moscone South, Exhibition Level Room 9
Speaker (TV): Rich L. Dumene – Renesas Electronics Corporation
Test
Wednesday, Jul 10th
2:30pm – 2:45pm PDT
Leveraging Chatbots For Test Engineering
Location: Moscone South, Exhibition Level Room 9
Speaker (TV): Andy Kittross – Teradyne
Test
Wednesday, Jul 10th
2:45pm – 3:00pm PDT
Session 2 Review
Location: Moscone South, Exhibition Level Room 9
Session Moderator (TV): Trent Weaver – Teradyne
Test
Wednesday, Jul 10th
3:10pm – 5:00pm PDT
Test Vision Poster Session and Reception
Location: Moscone South, Exhibition Level Room 10
Session Moderator (TV): Stuart Pearce – AEM
TestNetworking
Wednesday, Jul 10th
3:10pm – 5:00pm PDT
An Innovative Method and Apparatus for KGSD Testing of 2.5D and 3D Stacked Dies
Location: Moscone South, Exhibition Level Room 9
Poster Presenter (TV): Calvin S. Park – AMT. CO. LTD.
Test
Wednesday, Jul 10th
3:10pm – 5:00pm PDT
Automated Test Equipment for Battery Management Systems: Challenges and Solutions
Location: Moscone South, Exhibition Level Room 9
Poster Presenter (TV): Sandeep L. D'Souza – Elevate Semiconductor
Test
Wednesday, Jul 10th
3:10pm – 5:00pm PDT
DPD (Digital Pre-Distortion) for RF Power Amplifier Test
Location: Moscone South, Exhibition Level Room 9
Poster Presenter (TV): Yichuan Lu – Advantest
Test
Wednesday, Jul 10th
3:10pm – 5:00pm PDT
Driving Better Test Efficiency through Test Data Feed Forward
Location: Moscone South, Exhibition Level Room 9
Poster Presenter (TV): Nelson K. Leung – Texas Instruments, Inc.
Test
Wednesday, Jul 10th
3:10pm – 5:00pm PDT
GaN FET (HEMT) Mass Production Test Challenges and Solutions at Wafer Level
Location: Moscone South, Exhibition Level Room 9
Poster Presenter (TV): Liu Huipeng – AccoTEST
Poster Presenter (TV): Su Yan – AccoTEST
Test
Wednesday, Jul 10th
3:10pm – 5:00pm PDT
Increasing Productivity Utilizing Capacitive and Resistive Semiconductor Wafer Measurement
Location: Moscone South, Exhibition Level Room 9
Poster Presenter (TV): Ken Ameika – Vitrek
Test
Wednesday, Jul 10th
3:10pm – 5:00pm PDT
IRIIS: Infrastructure for Real-time Inspection of Image Sensors
Location: Moscone South, Exhibition Level Room 9
Poster Presenter (TV): Takuro Iizuka – Fixstars Solutions
Poster Presenter (TV): Masaru Ito – Fixstars Solutions
Poster Presenter (TV): Ryan Pettibone – Fixstars Solutions
Poster Presenter (TV): Yojiro Sumi – Sony Semiconductor Solutions
Test
Wednesday, Jul 10th
3:10pm – 5:00pm PDT
Optical edge coupling method for fully automated PIC wafer-level testing
Location: Moscone South, Exhibition Level Room 9
Poster Presenter (TV): Dan Rishavy – FormFactor
Test
Wednesday, Jul 10th
3:10pm – 5:00pm PDT
Target aware static code analysis techniques leveraging Formal Methods for embedded code
Location: Moscone South, Exhibition Level Room 9
Poster Presenter (TV): Jason J. Landers – TrustInSoft
Poster Presenter (TV): Mike Shearman – TrustInSoft
Test
Wednesday, Jul 10th
3:10pm – 5:00pm PDT
Thermal Properties and Temperature-rise of High Frequency RF Transistors at sub-50 nm Length Scales
Location: Moscone South, Exhibition Level Room 9
Poster Presenter (TV): John Gaskins – Laser Thermal
Test
Wednesday, Jul 10th
3:10pm – 5:00pm PDT
These Devices are Out of Control: Advanced Thermal Control Strategies for Tomorrow Devices
Location: Moscone South, Exhibition Level Room 9
Poster Presenter (TV): Kevin A. Thompson – Teradyne
Test
Wednesday, Jul 10th
3:40pm – 5:00pm PDT
Optimizing Semi Testing: A Decision-Making Framework with Physics-Informed ML and Causal Inference
Location: Moscone South, Exhibition Level Room 9
Poster Presenter (TV): Katie Monroe – Teradyne
Test
Thursday, Jul 11th
9:00am – 11:30am PDT
Test Vision Session 3: Digital Test Initiatives and Innovation
Location: Moscone South, Exhibition Level Room 9
Session Moderator (TV): Lauren Getz – Teradyne
Test
Thursday, Jul 11th
9:00am – 10:00am PDT
Test Floor 2030 – Scaling to meet the needs of Power and Mixed Signal Test
Location: Moscone South, Exhibition Level Room 9
Keynote Speaker (TV): Deidrick Solomon – Renesas
Test
Thursday, Jul 11th
10:00am – 10:15am PDT
Chiplet Ecosystem Testability for HVM
Location: Moscone South, Exhibition Level Room 9
Speaker (TV): Bob Bartlett – Advantest Corporation
Test
Thursday, Jul 11th
10:15am – 10:30am PDT
Advanced Probe Card Solutions to address HBM wafer and stacked die test challenges.
Location: Moscone South, Exhibition Level Room 9
Speaker (TV): David S. Cooke – FormFactor Inc.
Test
Thursday, Jul 11th
10:30am – 10:45am PDT
Singulated Die Sort as a tool to enable high precision thermal control for test of semiconductors
Location: Moscone South, Exhibition Level Room 9
Speaker (TV): Jaime Sanchez – Intel Corporation
Test
Thursday, Jul 11th
10:45am – 11:00am PDT
Test hardware Signal integrity design for soc package with ip specific impedance. :
Location: Moscone South, Exhibition Level Room 9
Speaker (TV): Noel I. Del Rio – NXP Semiconductors
Test
Thursday, Jul 11th
11:00am – 11:15am PDT
The Challenges in finding Chips that are Susceptible to Silent Data Errors
Location: Moscone South, Exhibition Level Room 9
Speaker (TV): Alan P. Aronoff – Tartan Silicon Systems, Inc.
Test
Thursday, Jul 11th
11:15am – 11:30am PDT
Session 3 Review
Location: Moscone South, Exhibition Level Room 9
Session Moderator (TV): Lauren Getz – Teradyne
Test
Thursday, Jul 11th
12:45pm – 2:45pm PDT
Test Vision Session 4: Test Data and Test Generation Enhancements
Location: Moscone South, Exhibition Level Room 9
Session Moderator (TV): Rich L. Dumene – Renesas Electronics Corporation
Test
Thursday, Jul 11th
12:45pm – 1:30pm PDT
From Vision to Reality: The CHIPS Act One Year Later
Location: Moscone South, Exhibition Level Room 9
Keynote Speaker (TV): Travis Mosier – mySilicon Compass
Test
Thursday, Jul 11th
1:30pm – 1:45pm PDT
Thermal Measurements at the Nano-scale: Theory, Reality, and Examples
Location: Moscone South, Exhibition Level Room 9
Speaker (TV): John Gaskins – Laser Thermal
Test
Thursday, Jul 11th
1:45pm – 2:00pm PDT
Risk Mitigation Strategies for mmWave Production Test Environments
Location: Moscone South, Exhibition Level Room 9
Speaker (TV): Ryan Garrison – FormFactor
Test
Thursday, Jul 11th
2:00pm – 2:15pm PDT
Extreme Temperature Automotive Testing
Location: Moscone South, Exhibition Level Room 9
Speaker (TV): Andrew Westall – Teradyne
Test
Thursday, Jul 11th
2:15pm – 2:30pm PDT
Reducing Complexity and Time-to-Market with Modern Approaches to Test Development
Location: Moscone South, Exhibition Level Room 9
Speaker (TV): Richard W. Fanning – Teradyne
Test
Thursday, Jul 11th
2:30pm – 2:45pm PDT
Session 4 Review
Location: Moscone South, Exhibition Level Room 9
Session Moderator (TV): Rich L. Dumene – Renesas Electronics Corporation
Test
Thursday, Jul 11th
2:50pm – 4:05pm PDT
Test Vision Panel Session: A Foundation for a Data Driven Future: How To Define, Adapt, and Adopt Standards To Enable a More Intelligent Test Flow and Seamless Operations
Location: Moscone South, Exhibition Level Room 9
Test
Thursday, Jul 11th
3:00pm – 4:00pm PDT
Test Vision Panel Session: A Foundation for a Data Driven Future: How To Define, Adapt, and Adopt Standards To Enable a More Intelligent Test Flow and Seamless Operations
Location: Moscone South, Exhibition Level Room 9
Panel Moderator (TV): Paul Berndt – Microsoft Corporation
Panelist (TV): John Yi – AMD
Panelist (TV): Mark Kahwati – Teradyne
Panelist (TV): Ken Butler – Advantest
Panelist (TV): Marco Marienberg – Qualcomm
Panelist (TV): Wes Smith – Galaxy Semiconductor
Panelist (TV): Mark D. Roos – Roos Instruments
Test
Thursday, Jul 11th
4:00pm – 4:05pm PDT
Closing Remarks
Location: Moscone South, Exhibition Level Room 9
Session Moderator (TV): Stuart Pearce – AEM
Test